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| wv3eg264m72esfr-d4 august 2005 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 2x64mx72 ddr sdram registered, w/pll description the wv3eg264m72esfr is a 2x64mx72 double data rate ddr sdram high density module. this memory module consists of eighteen 64mx8 bit with 4 banks ddr synchronous drams in fbga packages, mounted on a 200-pin so-dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option features 200-pin so-dimm, dual in-line memory module fast data transfer rates: pc2100 and pc2700 utilizes 266 and 333 mb/s ddr sdram components v cc = v ccq = 2.5v 0.2v bidirectional data strobe (dqs) option differential clock inputs (ck and ck#) dll to align dq and dqs transitions with ck programmable burst: length (2, 4, 8) programmable read# latency (cl): 2 and 2.5 (clock) serial presence detect (spd) with eeprom auto and self refresh: 64ms/ 8,192 cycle refresh gold edge contacts dual rank package option ? 200 pin so-dimm ? pcb C 31.75mm (1.25") max operating frequencies ddr333@cl = 2.5 ddr266@cl = 2 ddr266@cl = 2.5 clock speed 166mhz 133mhz 133mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2.5-3-3
wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin names pin name function a0-a12 address inputs ba0, ba1 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes ck0,ck0# clock inputs, positive/negative cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable v cc core power v ccq i/o power v ss ground sa0-sa2 eeprom address sda serial data input/output v ref input/output reference dm0-dm8 data-in mask v ccspd serial eeprom power supply scl serial presence detect(spd) clock input reset# reset enable nc spare pins, no connect pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7dq157v cc 107 a5 157 v cc 8dq558v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10/ap 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 cb0 121 cs0# 171 dq50 22 v cc 72 cb4 122 cs1# 172 dq54 23 dq9 73 cb1 123 nc 173 v ss 24 dq13 74 cb5 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dqs8 127 dq32 177 dq56 28 v ss 78 dm8 128 dq36 178 dq60 29 dq10 79 cb2 129 dq33 179 v cc 30 dq14 80 cb6 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 cb3 133 dqs4 183 dqs7 34 v cc 84 cb7 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 reset# 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram cs0# i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs s0# a0 serial pd a1 a2 sa1 sa2 scl sda wp dm dqs0 dm0 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s0# dm dqs4 dm4 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs s0# dm dqs1 dm1 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s0# dm dqs5 dm5 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqs s0# dm dqs2 dm2 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s0# dm dqs6 dm6 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqs s0# dm dqs3 dm3 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s0# dm dqs7 dm7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 cs1# i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dqs s1# dm dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqs8 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dm8 cs# dqs dm cs# dqs dm ddr sdram x 2 120 ohms ck0# pll ck0 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 register x 2 ddr sdrams ddr sdrams ddr sdrams v ccspd v ccq /v cc v ref v ss spd cs0# cs1# ba0-ba1 a0-a12 ras# cas# cke0 cke1 we# ba0-ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke: ddr sdrams cke: ddr sdrams we#: ddr sdrams rcs0# rcs1# rba0-rba1 ra0-ra12 rras# rcas# rcke0 rcke1 rwe# pck pck# reset# r e g i s t e r note: all resistor values are 22 ohms unless otherwise speci? ed. wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions 0c t a 70c parameter symbol min max unit note supply voltage (for device with a nominal v cc of 2.5v) v cc 2.3 2.7 i/o supply voltage v ccq 2.3 2.7 v i/o reference voltage v ref 0.49*v ccq 0.51*v ccq v1 i/o termination voltage (system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ccq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck# inputs v in (dc) -0.3 v ccq +0.3 v input differential voltage, ck and ck# inputs v id (dc) 0.3 v ccq +0.6 v 3 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver); v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver); v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver); v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver); v out = v tt - 0.45v i ol 9ma notes: 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulat ion. the ac and dc input speci? cations are relative to a v ref envelop that has been bandwidth limited to 200mhz. absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.3 v voltage on v cc & v ccq pin relative to v ss v cc , v ccq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c operating temperature t a 0 ~ +70 c power dissipation C 1gb single mezzanine memory p d 18 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. capacitance v cc 2.5v, v ccq = 2.5v 0.2v, t a = 25c, f = 1mhz parameter symbol min max units input capacitance (a0 ~ a12, ba0 ~ ba1,ras#,cas#, we# ) c in1 911pf input capacitance (cke0, cke1) c in2 911pf input capacitance ( cs0#, cs1#) c in3 911pf input capacitance ( clk0, clk0#) c in4 11 12 pf input capacitance ( dm0 ~ dm8) c in5 10 11 pf data & dqs input/output capacitance (dq0~dq63) c out1 10 11 pf data input/output capacitance (cb0 ~ cb7) c out2 10 11 pf wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr i dd specifications and conditions 0c t case < +70c; v ccq = +2.5v 0.2v, v cc = +2.5v 0.2v symbol conditions 335 262 265 unit i dd0 operating current - one bank active-precharge; t rc = t rc (min); t ck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,215 1,215 1,080 ma i dd1 operating current - one bank operation; one bank open, bl = 4, reads - refer to the following page for detailed test condition 1,485 1,485 1,350 ma i dd2p percharge power-down standby current; all banks idle; power - down mode; cke = wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters 0c t case < +70c; v ccq = +2.5v 0.2v, v cc = +2.5v 0.2v parameter symbol 335 262 265 unit min max min max min max row cycle time t rc 60 65 65 ns refresh row cycle time t rfc 72 75 75 ns row active time t ras 42 70k 45 120k 45 120k ns ras# to cas# delay t rcd 18 20 20 ns row precharge time t rp 18 20 20 ns row active to row active t rrd 12 15 15 ns write recovery time t wr 15 15 15 ns last data in to read command t wtr 111t ck col. address to col. address t ccd 111t ck clock cycle time cl=2.0 t ck 7.5 12 7.5 12 10 12 ns cl=2.5 6 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs-out access time from t dqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns output data access time t ac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput t dqsq 0.4 0.5 0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck ck to valid dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs-in setup time t wpre 000ns dqs-in hold time t wpre 0.25 0.25 0.25 t ck dqs falling edge to ck ris- t dss 0.2 0.2 0.2 t ck dqs falling edge from ck t dsh 0.2 0.2 0.2 t ck dqs-in high level width t dqsh 0.35 0.35 0.35 t ck dqs-in low level width t dqsl 0.35 0.35 0.35 t ck dqs-in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input t is 0.75 0.9 0.9 ns address and control input t ih 0.75 0.9 0.9 ns address and control input t is 0.8 1.0 1.0 ns address and control input t ih 0.8 1.0 1.0 ns data-out high impedence time from ck/ck# t hz +0.7 +0.75 +0.75 ns data-out low impedence time from ck/ck# t lz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns input slew rate (for input) t sl(i) 0.5 0.5 0.5 v/ns input slew rate (for i/o pins) t sl(io) 0.5 0.5 0.5 v/ns output slew rate (x4,x8) output slew rate matching t sl(o) 1.0 4.5 1.0 4.5 1.0 4.5 v/ns t slmr 0.67 1.5 0.67 1.5 0.67 1.5 note: ac speci? cations are based on micron components. other dram manufacturers speci? caitons may be different. wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters 0c t case < +70c; v ccq = +2.5v 0.2v, v cc = +2.5v 0.2v parameter symbol 335 262 265 unit min max min max min max mode register set cycle time t mrd 12 15 15 ns dq & dm setup time to dqs t ds 0.45 0.5 0.5 ns dq & dm hold time to dqs t dh 0.45 0.5 0.5 ns control & address input t ipw 2.2 2.2 2.2 ns dq & dm input pulse width t dipw 1.75 1.75 1.75 ns power down exit time t pdex 6 7.5 7.5 ns exit self refresh to non-read t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 tck refresh interval time t refi 7.8 7.8 7.8 us output dqs valid window t qh t hp -t qhs t hp -t qhs t hp -t qhs ns clock half period t hp t cl min or t ch min t cl min or t ch min t cl min or t ch min ns data hold skew factor t qhs 0.5 0.75 0.75 ns dqs write postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active to read with auto precharge command t rap 15 15 20 autoprecharge write recovery + precharge time t dal (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck note: ac speci? cations are based on micron components. other dram manufacturers speci? caitons may be different. serial present detect information byte # function described function supported hex value 265 262 335 265 262 335 0 de? nes # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram ddr 07h 3 # of row address on this assembly 13 0dh 4 # of column address on this assembly 11 0bh 5 # of module rows on this assembly 2 row 02h 6 data width of this assembly 64 bits 48h 7 data width of this assembly 00h 8 vddq and interface standard of this assembly sstl 2.5v 04h 9 ddr sdram cycle time at cas latency =2.5 7.5ns 7ns 6ns 75h 70h 60h 10 ddr sdram access time from clock at cl=2.5 0.75 0.75 0.7 75h 75h 70h 11 dimm con? guration type(non-parity, parity, ecc) ecc 02h 12 refresh rate & type 7.8us & self refresh 82h wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs serial present detect information (cont'd) byte # function described function supported hex value 265 262 335 265 262 335 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width x8 08h 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01h 16 ddr sdram device attributes: burst lengths supported 2,4,8 0eh 17 ddr sdram device attributes: # of banks on each ddr sdram 4 banks 04h 18 ddr sdram device attributes: cas latency supported 2,2.5 0ch 19 ddr sdram device attributes: cs latency 0clk 01h 20 ddr sdram device attributes: we latency 1clk 02h 21 ddr sdram module attributes registered address & control inputs and on-card dll 26h 22 ddr sdram device attributes: general +/-0.2v voltage tolerance c0h 23 ddr sdram cycle time at cl =2 10ns 7.5ns 7.5ns a0h 75h 75h 24 ddr sdram access time from clock at cl =2 0.75 0.75 0.7 75h 75h 70h 25 ddr sdram cycle time at cl =1.5 00h 26 ddr sdram access time from clock at cl =1.5 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 18ns 50h 50h 48h 28 minimum row activate to row active delay (=t rrd ) 15ns 15ns 12ns 3ch 3ch 30h 29 minimum ras to cas delay (=t rcd ) 20ns 20ns 18ns 50h 50h 48h 30 minimum active to precharge time (=t ras ) 45ns 45ns 42ns 2dh 2dh 2ah 31 module row density 512mb 80h 32 command and address signal input setup time 0.9ns 0.9ns 0.8ns a0h a0h 80h 33 command and address signal input hold time 0.9ns 0.9ns 0.8ns a0h a0h 80h 34 data signal input setup time 0.5ns 0.5ns 0.45ns 50h 50h 45h 35 data signal input hold time 0.5ns 0.5ns 0.45ns 50h 50h 45h 36-40 superset information (may be used in future) 00h 41 ddr sdram minimum active to active/auto refresh time (t rc ) 65ns 65ns 60ns 41h 41h 3ch 42 ddr sdram minimim auto-refresh to active/auto-refresh commmand period (t rfc ) 75ns 75ns 72ns 4bh 4bh 48h 43 ddr sdram maximum device cycle time (t ck max) 13ns 13ns 12ns 34h 34h 30h 44 ddr sdram dqs-dq skew for dqs and associated dq signals (t dqsqmax ) 0.50ns 0.50ns 0.45ns 50h 50h 45h 45 ddr sdram read data hold skew factor (t qhs ) 0.75ns 0.75ns 0.50ns 75h 75h 50h 46 reserved 00 00 00 00h 00h 00h 47 dimm height standard/low pro? le 01h 48-61 superset information (may be used in future) 00h 62 spd data revision code initial release 10h 63 checksum for bytes 0 ~ 62 69h 39h 6fh 64 - 127 manufacturer info 00h wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 67.60 (2.661) 63.60 (2.504) 1.0 0.1 (0.04 0.0039) 3.80 (0.150) max. 2.15 (0.085) 6.0 0.236 4.20 (0.165) 1.8 (0.071) 4.00 (0.158) min. 47.40 (1.866) 2- 1.80 (0.071) 11.40 (0.449) 13941 199 31.75 (1.25) full r 2x 2.40 (0.094) 4.00 0.10 (0.158 0.039) 20 (0.787) 2.45 (0.098) 4.00 0.10 (0.158 0.039) 1.00 0.1 (0.04 0.0039) 0.45 0.03 (0.018 0.001) 0.60 (0.024) 2.55 min (0.102 min) 0.25 (0.01) package dimensions for d4 * all dimensions are in millimeters and (inches) tolerances: 0.15 (0.006) unless otherwise speci? ed ordering information for d4 part number speed cas latency t rcd t rp height* wv3eg264m72esfr335d4-x 166mhz/333mb/s 2.5 3 3 31.75mm (1.25") wv3eg264m72esfr262d4-x 133mhz/266mb/s 2 2 2 31.75mm (1.25") wv3eg264m72esfr265d4-x 133mhz/266mb/s 2.5 3 3 31.75mm (1.25") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "-x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 e g 264m 72 e s f r xxx d4 -x g wedc memory ddr 2 gold depth (dual rank) bus width x8 2.5v fbga registered speed (mhz) package 200 pin so-dimm component vendor name (m = micron) (s = samsung) g = rohs compliant wv3eg264m72esfr-d4 august 2005 rev. 0 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 2x64mx72 ddr sdram registered, w/pll revision history rev # history release date status rev 0 created august 2005 advanced |
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